1. Field of the Invention
The present invention relates to output clock generation in high speed memory devices, and particularly in such devices having read latency greater than one output clock cycle.
2. Description of Related Art
Integrated circuits including high speed memory are operating at higher and higher clock rates. For example, some integrated circuits operate at 500 MHz and higher. At 500 MHz, a clock cycle is 2 nanoseconds, which approaches the propagation delays for signals on transmission lines on integrated circuits. Thus, clock timing and clock signal distribution problems arise at these high speeds. For high speed memories, read latencies can be more than one clock cycle.
In order to maintain high throughput in memories with read latencies that are more than one clock cycle, wave pipelining techniques are used. The pipeline allows output data to be supplied in each clock cycle, and absorbs the read latencies. In wave pipelines, the data being propagated in the memory is not latched during each clock cycle. Thus, the data can be considered to move in a “wave” through the device, which is basically mesochronous with the read clock.
In the design of clock circuits for high speed memories which use wave pipeline techniques, it is necessary to provide an output clock which matches output data with a mesochronous read clock more than one clock cycle earlier. Because of the mesochronous nature of the wave pipeline, and uncertainties in the propagation delays that occur on integrated circuits, the chips may provide output data within a tolerance that, depending on frequency, may be more than half a cycle wide. In this case, there may be both an up and a down transition in the clock within the acceptable tolerance for read latency. Thus, it is difficult to match the output data with the input read cycle in these circumstances.
Accordingly, it is desirable to provide techniques and architectures useful for output clock generation in a high speed, high-density memory device, which is suitable for use in wave pipeline architectures where read latencies may be more than one clock cycle long.